Packaging for semiconductor devices was rapidly becoming a significant % of the cost and footprint as die yield improved. Industry wide investment in packaging technologies was driving the potential to use the die itself as the package to enable smaller, thinner end user products and eliminate the cost of process steps and material.

Chip Scale Package (CSP) was a significant breakthrough in assembly technology with all the challenges of a developing process. Traceability would be critical for improving yield, reducing cost and realizing the expected benefits. The industry did not yet have a cost effective means of implementing traceability as there is no longer any package to mark!

Novel laser parameters were developed for marking processed silicon and integrated with a wafer handler to read in the wafer ID, retrieve the wafer map and correlate position using top side fiducials to accurately mark the backside of the die. System calibration schemes were developed for very small die (clocks) and maintain accuracy over time.

Implementing traceability for CSP enabled existing quality and reliability practices for the next generation IC packaging technology. Moving the process "upstream" to wafer form further reduced cost by removing rejects as early as possible in the process, eliminating waste for processing and potential for shipping bad parts to a customer. The system design enabled the company to compete very effectively in a significant market segment that had been the exclusive domain of a key competitor.